Nguyễn Đăng Chiến, Lưu Thế Vinh, Huỳnh Thị Hồng Thắm, Chun Hsing Shih


Hetero-gate dielectric (HGD) engineering not only suppresses the ambipolar current but also enhances the on-current of tunnel field-effect transistors (TFETs). Based on two-dimensional device simulations, we examined the roles and designs of hetero-gate dielectric structure in single- and double-gate TFETs. Proper comparisons and analyses show that the roles and designs of source-side dielectric heterojunctions are similar, whereas those of drain-side dielectric heterojunctions are extremely different in single- and double-gate TFETs. For both device structures, the optimal position of a source-side dielectric heterojunction does not depend on the ratio of low/high-k equivalent oxide thicknesses (EOTs). When increasing the EOT ratio, the on-current enhancement by an optimized source-side dielectric heterojunction is first increased (EOT ratio < 12) and then saturated (EOT ratio > 12). The role of a drain-side dielectric heterojunction in enhancing on-current is limited in double-gate TFETs (every EOT ratio), but significant in single-gate devices (EOT ratio < 12). For EOT ratios < 12, the optimal position of a drain-side dielectric heterojunction in double-gate TFETs is around 2-3 nm farther from the source compared to that in single-gate TFETs. For EOT ratios > 12, the optimal position of a drain-side dielectric heterojunction in double-gate TFETs is not dependent on the EOT ratio, unlike single-gate TFETs. Those differences are due to the difference in the depths of local potential wells in the two TFET structures.


Band-to-band tunneling; Double-gate transistor; Hetero-gate dielectric; High-k gate-insulator; Tunnel FET.

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DOI: http://dx.doi.org/10.37569/DalatUniversity.10.3.745(2020)


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