DIFFERENT ROLES AND DESIGNS OF HETERO-GATE DIELECTRIC IN SINGLE- AND DOUBLE-GATE TUNNEL FIELD-EFFECT TRANSISTORS
Keywords:Band-to-band tunneling, Double-gate transistor, Hetero-gate dielectric, High-k gate-insulator, Tunnel FET.
AbstractHetero-gate dielectric (HGD) engineering not only suppresses the ambipolar current but also enhances the on-current of tunnel field-effect transistors (TFETs). Based on two-dimensional device simulations, we examined the roles and designs of hetero-gate dielectric structure in single- and double-gate TFETs. Proper comparisons and analyses show that the roles and designs of source-side dielectric heterojunctions are similar, whereas those of drain-side dielectric heterojunctions are extremely different in single- and double-gate TFETs. For both device structures, the optimal position of a source-side dielectric heterojunction does not depend on the ratio of low/high-k equivalent oxide thicknesses (EOTs). When increasing the EOT ratio, the on-current enhancement by an optimized source-side dielectric heterojunction is first increased (EOT ratio < 12) and then saturated (EOT ratio > 12). The role of a drain-side dielectric heterojunction in enhancing on-current is limited in double-gate TFETs (every EOT ratio), but significant in single-gate devices (EOT ratio < 12). For EOT ratios < 12, the optimal position of a drain-side dielectric heterojunction in double-gate TFETs is around 2-3 nm farther from the source compared to that in single-gate TFETs. For EOT ratios > 12, the optimal position of a drain-side dielectric heterojunction in double-gate TFETs is not dependent on the EOT ratio, unlike single-gate TFETs. Those differences are due to the difference in the depths of local potential wells in the two TFET structures.
Appenzeller, J., Lin, Y.-M., Knoch, J., & Avouris, Ph. (2004). Band-to-band tunneling in carbon nanotube field-effect transistors. Physical Review Letters, 93(19), 1-4.
Bagga, N., Chauhan, N., Banchhor, S., Gupta, D., & Dasgupta, S. (2020). Demonstration of a novel tunnel FET with channel sandwiched by drain. Semiconductor Science Technology, 35, 1-7.
Beniwal, S. & Saini, G. (2019). L-shaped tunnelling field effect transistor with hetero-gate dielectric and hetero dielectric box. Paper presented at The 3rd International Conference on Trends in Electronics and Informatics, Tirunelveli, India. http://dx.doi.org/10.1109/ICOEI.2019.8862520.
Boucart, K. & Ionescu, A. M. (2007). Double-gate tunnel FET with high-κ gate dielectric. IEEE Transactions on Electron Devices, 54(7), 1725-1733.
Chien, N. D., Anh, T. T. K., Chen, Y.-H., & Shih, C.-H. (2019). Device physics and design of symmetrically doped tunnel field-effect transistors. Microelectronic Engineering, 216, 1-9.
Chien, N. D., & Vinh, L. T. (2013). Drive current enhancement in tunnel field-effect transistors by graded heterojunction approach. Journal of Applied Physics, 114(9), 1-6.
Choi, W. Y., Park, B.-G., Lee, J. D., & Liu, T.-J. K. (2007). Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Letters, 28(8), 743-745.
Duan, X., Zhang, J., Wang, S., Li, Y., Xu S., & Hao, Y. (2018). A high-performance gate engineered InGaN dopingless tunnel FET. IEEE Transactions on Electron Devices, 65(3), 1223-1229.
Hraziia, A. V., Amara, A., & Anghel, C. (2012). An analysis on the ambipolar current in Si double-gate tunnel FETs. Solid-State Electronics, 70, 67-72.
IEEE. (2020). International Roadmap for Devices and Systems. Retrieved from https://irds.ieee.org/.
Joshi, T., Singh, B., & Singh, Y. (2020). Controlling the ambipolar current in ultrathin SOI tunnel FETs using the back-bias effect. Journal of Computational Electronics, 19, 658-667.
Kane, E. O. (1961). Theory of tunneling. Journal of Applied Physics, 32(1), 83-91.
Koswatta, S. O., Lundstrom, M. S., & Nikonov, D. E. (2009). Performance comparison between p-i-n tunneling transistors and conventional MOSFETs. IEEE Transactions on Electron Devices, 56(3), 456-465.
Liu, C., Ren, Q., Chen, Z., Zhao, L., Liu, C., Liu, Q., … & Zhao, Q.-T. (2019). A T-shaped SOI tunneling field-effect transistor with novel operation modes. IEEE Journal of the Electron Devices Society, 7, 1114-1118.
Lyu, Z., Lu, H., Zhang, Y., Zhang, Y., Lu, B., Zhu, Y., … & Sun, J. (2020). Characteristic enhancement in tunnel field-effect transistors via introduction of vertical graded source. Chinese Physics B, 29(5), 1-6. Retrieved from http://cpb.iphy.ac.cn/article/2020/2030/cpb_29_5_058501.html
Mookerjea, S., & Datta, S. (2008). Comparative study of Si, Ge and InAs based steep subthreshold slope tunnel transistors for 0.25V supply voltage logic applications. Paper presented at The 66th Device Research Conference, California, USA. http://dx.doi.org/10.1109/DRC.2008.4800730.
Nayfeh, O. M., Hoyt, J. L., & Antoniadis, D. A. (2009). Strained-Si1-xGex/Si band-to-band tunneling transistors: Impact of tunnel junction germanium composition and doping concentration on switching behavior. IEEE Transactions Electron Devices, 56(10), 2264-2269.
Pandey, C. K., Dash, D. & Chaudhury, S. (2019). Approach to suppress ambipolar conduction in tunnel FET using dielectric pocket. Micro & Nano Letters, 14(1), 86-90.
Seabaugh, A. C., & Zhang, Q. (2010). Low voltage tunnel transistors for beyond CMOS logic. Proceedings of the IEEE, 98(12), 2095-2110.
Shih, C.-H., Chien, N. D., Tran, H.-D., & Chuan, P. V. (2020). Device physics and design of hetero-gate dielectric tunnel field-effect transistors with different low high-k EOT ratios. Applied Physics A, 126, 1-11.
Smets, Q., Verreck, D., Verhulst, A. S., Rooyackers, R., Merckling, C., Put, M. V. D., … Heyns, M. M. (2014). InGaAs tunnel diodes for the calibration of semi-classical and quantum mechanical band-to-band tunneling models. Journal Applied Physics, 115, 1-9.
Synopsys. (2013). MEDICI User’s Manual. California, USA: Synopsys Publishing.
Sze, S. M. (1981). Physics of Semiconductor Devices (2nd ed.). New Jersey, USA: John Wiley & Sons Publishing.
Toh, E.-H., Wang, G. H., Samudra, G., & Yeo, Y.-C. (2007). Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization. Applied Physics Letters, 90, 1-3.
Toh, E.-H., Wang, G. H., Samudra, G., & Yeo, Y.-C. (2008). Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications. Journal Applied Physics, 103, 1-5.
Wang, P.-F., Hilsenbeck, K., Nirschl, Th., Oswald, M., Stepper, Ch., Weis, M., … & Hansch, W. (2004). Complementary tunneling transistor for low power application. Solid-State Electronics, 48(12), 2281-2286.
Xu, H. F., Cui, J., Sun, W., & Han, X. F. (2019). Analysis of non-uniform hetero-gate-dielectric dual-material control gate TFET for suppressing ambipolar nature and improving radio-frequency performance. Chinese Physics B, 28(10), 1-14.
Volume and Issues
Copyright & License
Copyright (c) 2020 Nguyễn Đăng Chiến, Lưu Thế Vinh, Huỳnh Thị Hồng Thắm, Chun-Hsing Shih.
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.